Compact hardware architecture for first one detector using priority-based uniform partition

This paper presents an optimized architecture for a first-one detector (FOD) using a uniform partition decoding scheme based on the statistical distribution of the input code words. The proposed architecture uses a conventional method to optimize the Boolean expression of the input code words. Experimental results show that the proposed approach covers only 58 gates in a 0.25 m CMOS technology. Based on the result of our design, we can achieve a remarkable reduction of a hardware cost, which consumes less than 10% of the size of the implementation of previous works.