Scalability of split-gate charge trap memories down to 20nm for low-power embedded memories

In this work, split-gate charge trap memories with electrical gate length down to 20 nm are presented for the 1
^st
time. Silicon nanocristals (Si-ncs), or silicon nitride (Si
₃
N
₄
) and hybrid Sinc/SiN based split-gate memories, with SiO
₂
or Al
₂
O
₃
control dielectrics, are compared in terms of program erase and retention. Then, the scalability of split-gate charge trap memories is studied, investigating the impact of gate length reduction on the memory window, retention and consumption. The results are analyzed by means of TCAD simulations.