Design of high frequency phase locked loop

A digital phase-locked loop (DPLL) is designed using 0.18 mm CMOS process and a 3.3 V power supply. It operates in the frequency range 200 MHz-1 GHz. The DPLL operation includes two stages: (i) a novel coarse-tuning stage based on a flash algorithm, and (ii) a fine-tuning stage similar to conventional DPLLs. The flash portion of the DPLL is made up of frequency comparators, an encoder and a decoder which drives a multiple charge pump (CP)/low pass filter (LPF) combination. Design considerations of the flash DPLL circuit components as well as implementation using Tanner design tools are presented. Spectra simulations were also performed and demonstrated a significant improvement in the lock time of the flash DPLL as compared to the conventional DPLL.