SET characterization and mitigation in RTAX-S antifuse FPGAs

Heavy-ion test results utilizing novel test methodologies of non-volatile antifuse-based FPGAs are presented and discussed. In particular, the programmable architectures in the RTAX-S FPGA-family including the I/O structures, and the FPGA core were tested and their cross-sections measured. Previously available SET mitigation solution based on SET filtering was implemented on the RTAX-S test designs and their efficacy proven to reduce the saturation cross-section and increase the LET threshold of the mitigated test designs.