Pattern-directed circuit virtual partitioning for test power reduction

For a large circuit under test (CUT), it is likely that some test patterns result in excessive power dissipations that exceed the CUT’s power rating. Designers may resort to lowpower automatic test pattern generation (ATPG) tools to solve this problem, which, however, usually leads to larger test data volume and requires extra computational effort, even if such tools are available. Another method is to partition the circuit into multiple subcircuits and test them separately. Unfortunately, this usually involves rerunning the time-consuming ATPG for each partitioned subcircuit and solving the problem of how to achieve an acceptable fault coverage for the glue logic between subcircuits. In this paper, we propose a novel low-power virtual test partitioning technique without the above-mentioned shortcomings. The basic idea is to partition the circuit in such way that the faults in the glue logic between subcircuits can be detected by patterns with low power dissipation that are applied at the entire circuit level, while the patterns with high power dissipation can be applied within a partitioned subcircuit without loss of fault coverage. Scan chain routing cost has also been considered during the partitioning process. Experimental results show that the proposed technique is very effective in reducing test power.