Implementation of Finite State Machines on a Reconfigurable Device

We present a novel method for the implementation of Finite State Machines (FSM) using a reconfigurable architecture. The proposed method utilises run-time reconfiguration to reduce the hardware required t o implement FSMs. This is achieved through the use of a unique representation of the FSM which allows the next state of the state machine t o be calculated solely from the primary inputs rather than the primary inputs and the current state as would be traditionally required. This reduction i n parameters significantly reduces the size of the hardware block required to calculate the next state.