A manufacturable 0.30 /spl mu/m gate CMOS technology for high speed microprocessors

A 0.30 /spl mu/m gate CMOS technology for high speed microprocessors with five levels of interconnect is described. A primary challenge in developing a manufacturable 0.30 /spl mu/m gate CMOS process is gate length control. A detailed investigation of the sources of gate length variation using a specially designed testchip is presented. Linewidth control of /spl plusmn/10% is achieved using I-line lithography by applying optical proximity correction to the gate reticle. A high speed cache memory for the target 250 MHz microprocessor product has an access time of 2.02 ns from clock to data out.