Clock-Feedthrough Cancellation with Compensation Circuit for Switched-Current Systems

A novel switched-current memory cell is presented. The proposed circuit with compensation can effectively achieve the clock-feedthrough cancellation. Comparing with the original reduction circuit, the linear gain error, THD, and the offset error are significantly reduced without complicated device matching. The performance of the proposed circuit is verified using tsmc 0.35-μm CMOS process with 3.3V supply.