Nanocore/CMOS hybrid system-on-package (SoP) architecture for autonomous error-tolerant (AET) cellular array network

In this paper, the nanocore/CMOS hybrid system-on-package (SoP) autonomous error-tolerant (AET) cellular network architecture, which integrates today's mature CMOS technology with emerging nanotechnology, is proposed. Within the cellular network, each AET cell contains a nanocore, CMOS cell peripherals and their interface circuits in a silicon platform. The overall network is homogeneous. These imply strict constraints for intercellular connection schemes and routing policies. Depending on the communication requirement between two nodes.