Trench isolation for 0.45 /spl mu/m active pitch and below

A trench isolation technology which realizes a 0.45 /spl mu/m active pitch while maintaining latch-up holding voltage above 3.0 V for n+/p+ spaces /spl ges/0.6 /spl mu/m for 0.35 /spl mu/m deep trenches is described. Process optimization yields superior gate oxide (t/sub ox/=55 /spl Aring/) and diode performance comparable to LOCOS type isolations. Inverse narrow width effects are minimal at 30 mV (PMOS) and 100 mV (NMOS) for channel widths down to 0.17 /spl mu/m. Anomalous MOSFET sub-threshold conduction due to field crowding at the active edge has been avoided. The variation of field oxide thickness is 40 nm within a wafer and 10 nm within a 15 mm square die.