Rescheduling transformations for high level synthesis

A new approach is presented to high-level synthesis with self-testability. The motivation for this work is the need to fill the void between the fields of high-level synthesis and design for testability. The approach is based on a new allocation algorithm that maps a scheduled data-flow representation of the behavior into a data-path structure that is testable, with no need for test hardware insertion. An important feature of the approach is the rescheduling of transformations to perform design space exploration, under area, delay, and testability constraints. A significant advantage of this method is that the testability design is well integrated into the framework of high-level synthesis at the behavior level.<
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