Layout synthesis of combinational blocks from behavioral hardware descriptions

A CAD tool that generates the layout of a combinational circuit from a behavioral hardware description language (HDL) representation is presented. A minimized transistor netlist is synthesised. Simulated annealing is used to determine the optimal placement and routing of each transistor group. As input, the system accepts VHSIC hardware description language (VHDL), VERILOG, truth table, and Boolean equation descriptions. For simulation purposes SPICE models of the circuit are also generated.<
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