A synthesis algorithm for pipelined data paths with conditional module sharing

The problem of pipelined data path synthesis in VLSI design is investigated. Given the behavioral description of the circuit to be synthesized, in which one or more conditional branches may be nested, the authors propose a heuristic algorithm, which takes the mutual exclusiveness of conditional branches into account so that more than one operation shares a hardware module, and hence a chip with small size will be produced. Experimental results show that the proposed heuristic algorithm efficiently produces a nearly optimum solution. The authors present a conditional resource sharing algorithm which simultaneously determines resource sharing and pipeline scheduling. The algorithm is based on a module sharing graph, in which each vertex corresponds to a pair of operators that may share a hardware module. With the module sharing graph, the conditional resource sharing problem is reduced to the problem of finding a set of paths on the module sharing graph. The proposed algorithm does not need user interaction, and hence no careful adjustment of parameter values is needed. Experimental results show that the proposed heuristic algorithm efficiently produces a nearly optimum solution.<
>