Decoder Implementation of Spatially Coupled LDPC Codes

In order to meet the requirements of high reliability and high flexibility of wireless communication, the Space-coupled Low-Density Parity-Check (SC-LDPC) codes are deeply studied. At present, the main research direction of SC-LDPC codes is to reduce the complexity of the algorithm and reduce the occupation of decoding resources. In terms of hardware implementation, there is relatively little research. Therefore, in view of the above problems, considering hardware resource occupation and coding and decoding performance, the FPGA design and implementation of the SC-LDPC code codec are carried out, and the functional correctness test is carried out on the Xilinx xc7k325tffg900-2 chip.