VLSI Implementation of QRS Complex Detector Based on Wavelet Decomposition

This paper presents a very large–scale integration chip for a novel discrete wavelet transform (DWT) based QRS complex detection algorithm. In many aspects of electrocardiogram (ECG) analyses, QRS complex detection is the first step. For example, heart rate variability (HRV) is evaluated based on the RR interval and thus, an accurate QRS detection algorithm would substantially affect the subsequent steps in HRV analysis. On the other hand, since wireless monitoring currently remains prohibitively expensive and lowering the cost and power consumption of wireless monitoring depends upon a reduction in the complexity of the algorithm, in this study we propose a simple, reliable, low power and cost-effective QRS detection method and its VLSI implementation. Here, the task of the QRS complex detection is performed using the quadratic spline wavelet transform based wavelet packet decomposition. After a four-level DWT decomposition, in order to enhance the QRS complex a novel noise level detection is then performed. The proposed noise level detector would select two of the four wavelet coefficients and then calculate their product. As a result, in addition to DWT, the processing stage includes the product of the two selected wavelet coefficients, adaptive thresholding scheme, and the execution of decision rules. Fabricated on an 0.18-
$\mu \text{m}$
complementary metal oxide semiconductor, the 1-KHz processor draws only
$4.2~\mu \text{W}$
of power, and the chip area is only
$0.83~mm^{2}$
. Also, the detection accuracy of the proposed method is further verified using 48 recordings from the MIT-BIH arrhythmia database (Se = 99.57%,
$+\text{P}\,\,= 99.59\%$
), suggesting that the proposed QRS detector may achieve a high accuracy and cost-effective QRS complex detection.