A QSPI Interface Supporting ‘Bits-Decoding’ for High-Speed Access to Flash

A QSPI interface is proposed for accessing QSPI flash in this paper. This proposed QSPI interface transmission information for the master supports access to 3 types of flash by using the Bit-decoding algorithm, that is, the data is received from MSB to LSB in order into the master. This QSPI interface includes SPI mode, DSPI mode and QSPI mode. The SPI mode has 4 clock modes to switch, for receiving and transmitting the information. The DSPI mode and QSPI mode is utilized when needed for high-speed access to flash. Based on the QSPI transmission protocol, a finite state machine is used in this QSPI interface design, which to control the transmission timing. The design is verified through RTL simulation. The simulation result shows the correct functions and transports stable data.