Trapping of Hot Carriers in the Forksheet FET Wall: A TCAD Study

We simulate the spatial profile of trapped charge in the forksheet FET wall under hot-carrier stress by calculating carrier distribution functions and using a non-radiative multiphonon model. We observe charge trapping above and below the horizontal projection of the sheet in the wall. We find the charge profile not to depend on the sheet width and the trapping in the forksheet FET wall to be significantly smaller than the trapping in the gate stack.