FPGA Based Simulation Study of Wear-Leveling Block Searching Algorithm

Phase Change Random Access Memory (PCRAM) is a promising non-volatile memory device due to its attractive properties such as low power, fast access time, high storage density and bit addressability. However, PCRAM suffers from its weakness in endurance. Wear-leveling algorithm research become one of the most important topics of PCRAM application. FPGA based MMU implementation is a bridge to connect IoT terminal MCU with PCRAM. Usage index based block searching algorithm is the most important and fundamental step in PCRAM wear-leveling algorithm implementation. Based on our previous research on the storage and computation integrated architecture of IoT terminal, this paper proposes a FPGA based simulation study on PCRAM wear-leveling block searching algorithm for the first time. High Level Synthesis (HLS) based experiments and algorithm simulations are carried out. Simulation results show that the proposed FPGA hardware block searching algorithm can be effectively implemented, thus, enables a better wear-leveling algorithm implementation to improve endurance of PCRAM in IoT terminal applications.