Performance Analysis of Various CMOS SRAM Cells

Low-power integrated circuits are in high demand due of the wide variety of electronic portable devices for which they are used. SoC (System on Chips) power consumption and speed are both determined by on-chip SRAM (Static Random Access Memory) performance. We have been making CMOS devices smaller for almost 50 years to make them more portable and small and to improve their performance in terms of access time, power use, latency, and other factors. Low supply voltage and leakage energy have been the primary focus due to the potential for dramatically lower power usage. Along with the leakage power, power consumption and speed are the main considerations for chip design. This article covers the simulation of 6T, 7T, and 8T SRAM cells utilizing low power reduction approaches and builds a modified model that offers the user with a product that costs less and has decreased power delay. SRAM cells in various configurations (6T, 7T, and 8T) have been constructed and compared using read delay, write delay, and leakage reduction strategies as the foundation for our research here.