Optimal Test Sequences for Logic Verification closure in State Dependent RTL Digital designs

Semiconductor applications demand shorter time-to-market with ever-increasing design complexity for any given digital design consisting combinatorial logic and finite state machines (FSMs). This conundrum results in unforgiving development schedule and specifically impacting digital design logic verification schedule and verification quality in terms of coverage goals (code/functional/state). EDA Tool industry is driving the concept of Logic Verification closure utilizing the Constrained Randomization based on Tool’ Random Seed Capability and Verification Methodology or Mathematical Verification techniques. Thereby EDA tools are poised to generate exhaustive logic test sequences or logical mathematical conditions (known as properties) to achieve logic verification coverage goals over a period of test regressions or property evaluations. In this work, a formulated approach is discussed in each digital design with combinatorial logic and finite state machines (FSMs)to create optimal test sequences by taking into calculation of input design under test (DUT) states, design feature space, randomized input scenario space with constraints and test combinations.