Existence of Single-Event Double-Node Upsets (SEDU) in Radiation-Hardened Latches for Sub-65nm CMOS Technologies

A single-event double-node upset (SEDU) may appear to result in an erroneous state of the storage element due to the scalability of transistor features. Therefore, SEDU must be well addressed from the perspective of circuit reliability, especially for safety-critical electronics. Some previous studies claimed to protect against SEDUs in 65-nm process technologies, but were not thoroughly verified. To better understand the technology-scaling impact, we re-examine SEDU in different advanced technologies (including 7-nm finFET, 45-nm bulk CMOS, and 65-nm bulk CMOS). An integrated multi-level framework is developed with the current-source modeling derived from the device-level TCAD simulation, combined with voltage calculation derived from the circuit-level SPICE simulation. To adequately capture the probability of errors occurring in the latch design under all possible scenarios, this paper also considers a variety of environmental factors, such as strike angles, temperature variation, and technology nodes. Also, three classical latch designs (i.e., TMR, DICE, and HLR) have been implemented in different technologies and well calibrated for experiments. According to experiment results, it is evident that SEDU is highly dependent on both the physical layout of the design as well as its design style. DICE is found to be the most susceptible to SEDU in all three manufacturing technologies, whereas TMR and HLR can be immune to SEDU in the 45-nm and 65-nm technologies due to a lack of sufficient charge to upset more than two nodes. It is, therefore, essential to consider both the physical layout and the manufacturing technology employed for ensuring the robustness of a radiation-hardened design against particle strikes.