High-Coverage DfT and Reliability Enhancements for Automotive Floating Gate OTP Beyond AEC-Q100

The increasing power supply demands of automotive SoCs that run ADAS applications require a high degree of configurability and trimmability of the Power Management Integrated Circuits (PMICs) that runs it. Thousands of configuration and trim bits are required that need non-volatile storage on-chip. The most trusted memories are based on floating gate (FG) technology. Automotive fitness of such non-volatile memory (NVM) is predominantly judged by its qualification status as per AEC-Q100. Whilst this is undeniably important, high-quality applications need test modes for every block, even the often “forgotten” digital decode and control logic, which in turn control test modes. A few examples show that without logic test even gross faults can escape the functional test of the NVM. The paper describes how a commercially successful OTP (One Time Programmable NVM) architecture with a proven track record in the consumer domain is enhanced to serve most demanding automotive applications in terms of test quality (coverage), reliability and functional safety (FuSa). It includes redundancy and stress modes for the memory array, reliability enhancements of the analog reference circuits, and digital test modes addressing any digital inside the entire OTP block.