A 5.0-to-12.5-Gb/s, 1.7-pJ/b, 0.66-μs Lock-time Reference-less Sub-sampling CDR with Beat Detection FLL in 28nm CMOS

The primary role of a frequency-locked loop (FLL) is to match the frequency of the recovered clock to the bit-rate clock frequency. Since a perfect match is impossible, there is always a residual frequency even after the FLL is locked. This residual frequency is compensated within the capture range of the phase detector (PD). In practice, the capture range of the PD is usually narrow, and it is desirable to reduce the residual frequency of the FLL as much as possible without sacrificing lock-time, frequency coverage, and energy efficiency.