A 17-21GHz Current-Folding Frequency Tripler With >36 dBc Harmonic Rejection in 90nm CMOS

Frequency multipliers (FM) following PLLs or VCOs are widely used to generate mm-Wave LO signals. A useful approach to achieve frequency multiplication is based on combining multi-phase input signals to remove all but the desired harmonics [1]. However, the main disadvantage of edge combining is that the achievable harmonic suppression is closely related to the precision of the phase shift progression between polyphase input signals, which is not readily available in mm-Wave. One of the simplest alternatives to implementing FM is to overdrive an amplifier and exploit its harmonic distortion to generate the desired output signal [2]. Self-mixing and injection-locked approaches are the common techniques for implementing FMs [3] –[7]. For example, the VCO should exhibit the fundamental $\omega_{0}$ and second-order harmonic $2 \omega_{0}$ components for self-mixing to produce the desired triple-frequency output $3 \omega_{0}$ from a bandpass filter (BPF). Although this approach has the advantage of simplicity, it usually exhibits limited suppression of harmonics, especially signal components at the input frequency.