Spike-CIM: A 290TOPS/W Spike-Encoding Sparsity-Adaptive Computing-in-Memory Macro with Differential Charge-Domain Integrate-and-Fire

Computing-in-memory (CIM) is a promising candidate for edge node processors by alleviating power-hungry memory access bottleneck [1 – [6]. While earlier CIM macros focused on efficient multiplication-accumulation (MAC) operations, recent works exploit neural network (NN) sparsity to further reduce the macro energy [1] [2] (Fig.1 top left). Nevertheless, it relies on digital cores to actively monitor system sparsity, bringing extra system-level complexity [1]. An ADC skipping technique performs early termination when the MAC output is small [2]. Yet, the current-mode operation degrades PVT robustness. Besides, both of the works require multi-bit SAR ADCs for quantization, inducing area overhead. The integrate-and-fire (IAF) CIM enables sparsity-adaptive computation and multi-bit quantization while requiring only a single comparator [3]. But the current domain operation again leads to large performance variations.