A 12.8-Gbps 0.5-pJ/b Encoding-less Inductive Coupling Interface Using Clocked Hysteresis Comparator for 3D-stacked SRAM in 7-nm FinFET

3D-stacked memory plays a vital role in achieving high-throughput and low-power operation in various devices. The 3D integration of memory chips, such as SRAMs and DRAMs, enables high-bandwidth, large-capacity, and low-power memory. However, conventional wired integration using TSVs and $\mu -$bumps has challenges of additional TSV process cost, area overhead cost, and low yield [1–4]. Wireless integration using inductive coupling known as ThruChip Interface (TCI) has low cost and high yield thanks to its compatibility with standard CMOS fabrication processes [5]. Furthermore, a physical placement method of placing coils over SRAM macros proposed in [6] reduces the area overhead to just that of transceiver circuits while minimizing the resultant loss in communication efficiency. A synchronous transceiver topology is a key enabler for the method since it can detect the lower received amplitude due to the over-SRAM placement. In [6], Manchester encoding is employed to enable synchronous communication, but the data-rate is limited to 8.5 Gbps, where the distribution of the high-frequency clock required for encoding is the bottleneck. This paper proposes a new receiver circuit that eliminates the need for encoding, achieving a 12.8-Gbps data-rate.