A 7.5Gb/s/pin 12Gb-LPDDR5x SDRAM with a Pseudo-double-bit ECC and “Spider”-shape Datapath Control Architecture in a 2nd Generation 10nm DRAM Process

Applications in 5G wireless communication and edge computing require higher bandwidth and better power efficiency, which in turn driving fast iterations of low-power mobile memory products, from LPDDR4x running at 4.266Gb/s/pin to LPDDR5x at 7.5Gb/s/pin and above [1–2]. As feature size of DRAM technology is shrunk into 10 nm class, single bit fail becomes problematic and requires on-die error-correction code (ECC) to help mitigating yield loss. Due to die size restriction, only 1-bit ECC is generally implemented. In this paper, a 12Gb LPDDR5x SDRAM using a full-bank architecture with flexible T-shape Bit Lines (BL) is presented, along with unique pseudo-double-bit ECC functions. Equivalent 2-bit error can be corrected during one read operation, including some BL shorts. A “Spider”-shape eight-way multiplex is served as the central traffic control of the high-speed datapath. Read and Write traffic will be directed accordingly based on different bank architectures (8-bank or 4-bank-group) or configurations (x16 or x8). Link ECC is incorporated into the datapath to facilitate another level of protection for data integrity. A direct dynamic voltage and frequency scaling (DVFS) is proposed to further cut down power consumption when level shifters are removed while crossing different voltage domains. Dual-tail high-speed data receivers [3] incorporated both 1-tap DFE (decision feedback equalizer) and offset-cancellation is presented along with a proposed on-die eye monitor (ODEM), to evaluate data eye margin with an emulated channel response.