A 0.95pJ/b 5.12Gb/s/pin Charge-Recycling IOs with 47% Energy Reduction for Big Data Applications

High bandwidth memory (HBM) is crucial in processing big data in realtime, yet its massive dynamic power consumption is an issue (Fig. 1). With IO capacitances $(\mathrm{C}_{IO})$ reaching up to 2.4 pF [1], over 1000 TSVs would readily heat the stacked dies and exceed the package power budget, further degrading the performance. A spiral point-to-point TSV structure [2] reduces the parasitic loads per IO by increasing the slew rate to minimize energy. However, this is only applicable in die-to-die 3Dstack structure and is not suitable for the more generic IO, e.g., transmission line link (DDR $5 \mathrm{C}_{IO} \sim 0.9$ pF [3]). HBM2E lowers VDD from 1.2V to 1.1V [4], however, the dynamic power bottleneck still exists in the ever-increasing speed and limitation of VDD and load scaling down. Adiabatic stepwise charging [5] was proposed to reduce the energy per transition for the clock tree. Nevertheless, this method only applies to the periodic clock rather than random data pattern and needs capacitor tanks which are neither affordable in today’s high-density or high-speed IOs. To address this data transition energy problem, this paper presents two Charge-Recyclsssing (CR) IOs, single-channel (CR1) and multi-channel (CR2/4/8), which apply to both TSV and 50-Ohm matched transmission-line (T-Line) links.