A Local Transpose 9T SRAM Compute-In-Memory Macro with Programmable Single-Slope SAR ADC

With the explosion of data and comprehensive utilization of artificial intelligence (AI) algorithms for data processing, the traditional computing system faces high-speed processing challenges. However, the conventional Von Neumann computing systems with separated computation and storage units cannot achieve satisfying performance. Compute-in-memory (CIM), as a promising and attractive method, is highly introduced. Most reported works have focused on conducting forward data propagation for inference [1]–[2]. However, in the neural network training stage, backward error propagation, similar to the forward operation, occupies a significant processing time and power consumption for updating the weights. Transpose CIM with two-directional access can be utilized in both inference and training stages as illustrated in Fig. 1. A group of SRAM bit-cells combined with an additional two-directional processing unit is engaged in recent transpose SRAM CIM works. An additional processing unit requires more than one bit-cell area, leading to a large overhead area. Even though the CIM macros in [3]–[4] show successful transpose operation, the shared transpose processing unit generates limited processing throughput.