A 6-bit 5.12-GS/s Flash ADC with Track-and-Hold Embedded Dynamic Preamplifier in 28nm CMOS

As emerging applications require a high data-rate communication, ADCs for these systems should have a multi-GHz signal bandwidth [1]. Typically, a flash ADC is the most widely used structure for the GHz ADC thanks to 2
^N
-1 comparators deployed in parallel for an N-bit operation. Flash ADCs usually adopt a track-and-hold (T/H) at the frontend to sample its high-speed inputs before the quantization, and thus the frontend T/H often limits the speed and resolution of the ADCs [1–4]. In addition, a dedicated time for the T/H should be compromised with comparators’ operation time out of the given sampling period. This work presents a 6-bit 5.12 GS/s flash ADC with T/H-embedded dynamic preamplifier. Without having a dedicated T/H, the first preamplifiers sample the input signal at the output and then the amplified signal is transferred to the subsequent stage within one clock period in a pipeline fashion. The dynamic preamplifiers consist of two stages. Each preamplifier stage is interpolated by a factor of 2, thus resulting in 4× interpolated preamplifiers for 6-bit flash ADC. Consequently, the prototype ADC achieves an SNDR of 32.97dB and SFDR of 41.52dB at 5.12 GS/s.