A D-Band Packaged CMOS Integrated Transmitter for MU-MIMO Applications

Growing demand for data across all communication requires an increase in both of capacity and density of back-haul point-to-point (PTP) and point-to-multipoint (PTMP) data links [1]. A D-band (110-170GHz) phased-array transceiver offers an attractive means to increase the capacity by leveraging the large available bandwidth and overcomes the high free-space path loss by adopting large array gain. Recent advances in process scaling are enabling > 100GHz transceiver implementations in low-cost CMOS technologies for commercial applications. In addition, to meet the requirements of future commercial systems above 100GHz, a low-cost and high-performance packaging platform is required. Recent publications have demonstrated high performance D-band transceivers capable of high-order and wide-bandwidth modulation [1, 2, 3, 4, 5]. However, very few are packaged or are tested with an on-chip PLL.