Fault Securing Techniques for Yield and Reliability Enhancement of RRAM

Fault securing techniques based on address remapping (AR) for RRAM are proposed in this paper. We first classify the traditional RRAM fault models into 1-maskable fault and the 0-maskable fault types based on their fault effects. Therefore, the fault effects of most faulty cells can be masked before subject to the usage of ECC and hardware redundancies. Therefore, the burden of ECC and hardware redundancy techniques can be greatly reduced. The corresponding test and repair flow is also presented. A simulator is developed to evaluate the hardware overhead, repair rate, yield, and reliability. According to experimental results, we can enhance these measures significantly with almost negligible hardware overhead.