Area Efficient Asynchronous Circuits for Side Channel Attack Mitigation

Synchronous sequential or clocked digital circuits are susceptible to synchronized side channel attacks (SCAs). By distributing (in time) data processing, one method used to mitigate or defend against SCAs is clockless, asynchronous circuit design. A problem often associated with clockless, asynchronous circuit design methods, like Null Convention Logic (NCL), is the large area for logically equivalent circuits. Typical asynchronous circuits are 2.5 to 3.5x the size of their synchronous sequential counterparts. This work develops a data-path design methodology based on a library of unique hybrid cells (part conventional and part NCL). The new hybrid method has shown a significant reduction in transistor count for asynchronous circuits. It results in logically equivalent asynchronous circuits with only an average transistor count increase of 6% while maintaining distributed (in time) processing advantages. The method, hybrid gate description, and comparison for several benchmark circuits are presented.