AI-assisted Synthesis in Next Generation EDA: Promises, Challenges, and Prospects

Despite the great advance achieved by electronic design automation (EDA) tools, there is still a long way towards hardware agile development, whose ultimate goal is to reduce chip development cycles from years to months or even weeks. Hardware development typically involves many optimization-evaluation iterations, indicating that (1) fast and accurate quality-of-result (QoR) evaluation and (2) efficient optimization, either independently or integrally, will conspicuously improve the development efficiency. Specifically, targeting high-level synthesis and logic synthesis, we investigate (1) the power of exploiting graph neural networks (GNNs) for generalizable and accurate performance predictions, (2) the efficacy of applying reinforcement learning (RL) for design exploration, and (3) the superiority of combining GNN and RL to solve EDA problems. Experimental results demonstrate the promises of infusing intelligence into design synthesis and EDA tools. On top of current endeavors, we summarize the challenges in the respective EDA contexts and the prospects toward next generation EDA tools.