A Nano-Watt, Subthreshold Self-Biased CMOS Voltage Reference without Resistors and BJT

This paper introduces a novel and purely CMOS voltage reference for low-voltage and low-power applications. The proposed circuit takes advantage of the
$\text{AV}_{\text{GS}}$
of different-threshold transistors operating in subthreshold for
$\Delta \mathrm{V}_{\text{TH}}$
compensation. By stacking
$\Delta \mathrm{V}_{\text{GS}}$
, a higher reference voltage is obtained. No BJTs and resistors are used to minimize the area footprint. The proposed voltage reference is simulated in a triple-well 65nm technology. Simulation results highlight that the design can deliver an average VREF and temperature coefficient of 444.06 m V and
$\boldsymbol{71.20 \text{ppm}/^{\mathrm{o}}\mathrm{C}}$
, respectively, from −
$40^{\mathrm{o}}\mathrm{C}$
to
$\boldsymbol{125 ^{\circ}\mathrm{C}}$
after trimming. The measured line sensitivity is 0.569%/V from 0.8V to 1.2V. The circuit has a PSRR of −40.37 at 10Hz, −66.56 at 1kHz, and −93.84 dB at 1MHz. Additionally, the power consumed is only 1. 32nW at a supply of 0.8V.