Low Area Design Architecture of XOR-MUX Full Adder based Discrete Wavelet Transform

In the recent trends, development in digital technology has increased largely. High performance with fast response and small in terms of size are the critical requirements for the devices used for applications such as image processing and others. Because of the arithmetic operations of adders and multiplier designs, digital systems in VLSI implementation are prone to have higher crucial logic size. It requires plenty area and power consumption because of the usage of regular adders and multipliers. The fundamental architecture of the discrete wavelet transform (DWT), contains several level of filter banks. These filter banks are generally made of low pass and high pass filters owing to the decomposition of coefficients. In this paper, the work done is the implementation of DWT by modifying the regular summing units and repeated adders with XORMUX adders and Truncation multipliers. It brings down the logic required. Thus it reduces the area and power on the computations when compared to conventional adders and multipliers. Also there is about 41% reduction in the area occupied by DWT architecture compared to previous works.