Design of mixed-radix FFT algorithm based on FPGA

With the rapid development of digital signal processing technology in image processing, radar, communication, fast Fourier transform (FFT) has important research significance. FFT is a fast algorithm of discrete Fourier Transform (DFT). Based on FPGA chip, this paper implements FFT of 256 and 1024 points using pipeline architecture by combining the Mixed-Radix algorithm and Cooly-Tukey algorithm. The main work of this paper includes the optimization of data uploading and storage in FPGA chip, the architecture analysis of mixed-radix algorithm implementation, and the improvement of FFT data computing architecture. Full use of FPGA parallel processing, easy programming implementation, pipeline processing architecture and other advantages to achieve high-speed FFT calculation.