Design and Implementation of a K-Band Active Frequency Quadrupler with Low DC Power Consumption

In this study, a frequency quadrupler with low power consumption has been developed by using cost-effective packaged GaAs FET. Design requirements of the frequency quadrupler was to obtain output power above 1dBm for the input power of 5dBm at the 20GHz output frequency with minimum 20dBc harmonic rejection ratio (HRR). Output power require- ment is achieved for wide input power range, 0-9dBm. Taking advantage of the Class-B topology being rich in harmonics and having low DC power consumption, the frequency quadrupler is able to achieve 4.3dBm output power for 5dBm input power 20GHz output frequency with low DC power consumption such as 30mW. Additionally, the quadrupler has ability to have output power above 1dBm for 19.7-20.3GHz output frequency. Without the need for an external filter, good harmonic rejection ratios are obtained such as 24dBc, 27dBc, 23dBc, 28dBc and 22dBc on the fundamental, the second, the third, the fifth and the sixth harmonics respectively. The frequency quadrupler is preferable in mobile communication systems due to its low cost, low DC power consumption and high output power.