Low-power High-speed Folded MCML-based Frequency Divider for High-frequency Applications

This article presents a novel and robust approach for implementing low-power and high-speed Folded MOS Current Mode Logic (FMCML) based frequency dividers that can operate at higher frequencies. The proposed frequency dividers are designed with folded MCML logic-based D flip-flops. The D flip-flop is designed with the concept of using a D latch with a pulse generator unit where a novel circuit is proposed for the D latch. In some proposed frequency dividers, a CML buffer is introduced at the output of each flip-flop. The buffer at the output of each D flip-flop helps to reduce the distortion and solves the low output swing problem which is a common problem in the MCML topology. All the proposed circuits are implemented using 45nm technology in the Cadence Virtuoso tool. The performance of proposed frequency dividers is compared with conventional folded MCML-based frequency divider circuit based on various parameters like delay, power, output swing, power-delay product, maximum input clock frequency, and figure-of-merit. The performance analysis shows that the proposed folded MCML frequency divider circuits consume less power and exhibit a faster response compared to the conventional folded MCML circuits. One of the proposed frequency dividers can work for higher input frequencies up to 11 GHz, so it can also be used in high-frequency applications.