Area Reduction in Field Programmable Gate Array with Convolutional Neural Network

The term "Convolutional Neural Networks" (CNN) refers to a technique that is widely used in a variety of industries and has achieved promising results in recent years. Over ninety percent of the jobs that are performed by a CNN are convolutions. The most effective convolutional neural networks, or CNNs, often consist of a very large number of layers and filter weights, which results in a significant increase in the amount of work required for computation and communication. The present CNN-explicit accelerator is substantially more productive than its predecessors; nonetheless, it is often rigid or calls for a sophisticated regulator to manage the computation and data transmission motion of multiple CNNs. Utilizing the striding value will allow us to accomplish our primary goal, which is to minimize the height and breadth of the picture while simultaneously increasing the pixel intensity. Employing the stride values also helps to lessen the computational imbalance and the overlap that occurs as a result of using them. The suggested CNN accelerator based on FPGAs is composed of three primary levels, which are the convolution layer, the pooling layer, and the activation layer. Pixels that have been taken from the picture serve as the input for the accelerator. The design of the proposed FPGA-based CNN accelerator has been completed, and the performance parameters of the FPGA accelerator show that the novel multiplier approach improves the accelerator's speed by 55,43 percent while simultaneously reducing its power consumption by 64,12 percent in exchange for a larger footprint. The findings of the experiments indicate that the magnitude of the picture may be reduced by the incorporation of a multiplier array-based convolver into the architecture of the proposed accelerator.