Reconfigurable Clock Rate Based Synchronous Binary Counter

The need of high frequency and increasing applicability of the counters are the fundamental requirements for applications in VLSI. A Synchronous binary counter is required in many applications, such as telecommunications, clock dividers and watchdog timers to be fast and support a large bit-width. In order to lower the delay, power and adjust the counting speed of the design in comparison to the existing 64-bit Synchronous Binary Counter, the Reconfigurable Clock Rate based 64-bit Synchronous Binary Counter is introduced. The proposed reconfigurable clock rate based 64-bit synchronous binary counter uses a Johnson counter and a clock divider to decrease the complexity of the overall hardware, propagation delay produced by fan-outs, power consumption, with an increase in frequency. The proposed Reconfigurable Clock Rate Based 64-bit Synchronous Binary Counter is analyzed, implemented, verified and compared to the existing 64-bit Synchronous Binary Counter using Cadence RTL Compiler and Cadence Genus at 45 nm technology. In the proposed reconfigurable clock rate based 64-bit synchronous binary counter, i) Power consumption is decreased by 64.999% ii) Delay is decreased by 9.848% iii) overall Power Delay product is reduced by 68.447% when compared with existing 64-bit Synchronous Binary Counter. Where ever this proposed architecture is used in the applications like watchdog timer, measurement systems, the contribution of such architecture reduces the power delay product and hence achieving optimal power consumption and delay.