SONR based layout decomposition and applications

As the integrated circuit (IC) technology development moves forward, the design becomes more and more complicated, and the chip size becomes larger and larger. It’s getting more challenging to analyze the design and detect the potential manufacturing issues in an efficient way. The layout decomposition brings the possibility and flexibility to address the above challenges as the unique patterns after layout pattern decomposition reduce the number of wafer measuring sampling points and give the best coverage of the layout for a quick and effective design check. There are multiple ways to decompose a layout as stated in literatures, in this paper, we’ll introduce Siemens EDA’s machine learning technique named SONR for the layout decomposition and how it can be used to reduce OPC recipe development and tape-out cycle time.