FPGA Based DCO With Fine Control Correlation Calibration Technique

Digital controlled oscillators (DCOs) play an important role in all digital phase locked loop (ADPLL) performance. DCOs have many advantages compared to their voltage controlled oscillators (VCOs) analog counterparts, such as: their wide frequency and supply voltage range, smaller area and being fully synthesizable. This work presents an FPGA based DCO implementation for use in ADPLL. It also presents the calibration technique which solves the non-monotonicity problem between the control code and the oscillation frequency. The issue is observed when implementing fine control of the DCO using ring oscillator (generator on delays) which is implemented with 4 carry4 blocks and 16 input multiplexer within the seven series Xilinx FPGAs for minimum controlled delay. The work is implemented on an Artix7 Xilinx FPGA using NEXYS 4 development board from Digilent and measured performance using oscilloscope is presented. Comparison between the control code and frequency relation prior and after calibration is also shown.