Designing high quality test chips with improved coverage for design rule exploration, process variation improvement and hotspot discovery

A key challenge to new IC technology node development is the lack of quality and comprehensive layout that can effectively probe process capabilities, design and process interaction and disclose stress DR corners. At the very first stage of process development, process specifications need to be defined, RET (Resolution Enhancement Technique) recipes need to be specified, and design rule establishment is required to validate layout manufacturability. Each of these key works requires the availability of chip layouts to evaluate the quality, accuracy, and comprehensiveness of development results. This is a classic “chicken-and-egg” dilemma, we need layouts in order to develop the process, however, we also need as much information of the process and design rules, if not only a snapshot, before meaningful chip layout design could be carried out.An abundant variety of layouts shall be established, which would cover a span of design styles, in order to develop and test RET recipes and design rules properly. Yet, IC designers do not start developing layouts until AFTER actual process development has progressed, to a certain point that reasonable amount of understandings on manufacture capabilities and limitations are comprehended, and the ground design rules are appropriately established. Even then, it is only possible to get limited number of design layouts until further process maturity.In this work, we propose a synthetic layout generation methodology which delivers design patterns based on only ground design rules. The wide range of design patterns could be tested and evaluated to gain abundant information of the process, disclosing strengths and limitations, even before the manufacturing phase. This new approach brings high quality process development with remarkably reduced process development cycle time.