Design and Analysis of Groundless XNOR Gate topology in 90nm Technology

This paper presents the study of XNOR gate circuits and implementation of an improved version of groundless two-input XNOR gate. All the circuits are designed with the same design parameters for a valid comparison. Supply voltage and load capacitance are taken as 1V and 5fF, respectively. Simulation is done using Cadence Virtuoso with 90nm technology parameters. Detailed analysis is done regarding power consumption, propagation delay, power delay product, energy-delay product, and the number of transistors used for implementation. Improved version of groundless XNOR gate achieves up to 90.4% reduction in power consumption and 88.2% reduction in PDP. All other parameters are found to be improved with the new design except the area requirement. Moreover, the area required for an improved XNOR gate is less than the area requirement of CMOS based XNOR gate.