PCIe Transaction and Data link Layers Verification IP Development using UVM

In this publication, PCI Express Transaction Layer and Data Link Layer verification is carried out. The author provided detailed information regarding the Transaction Layer and Data Link Layer of PCI Express. The study developed the verification IP for Transaction Layer and Data Link Layer, wrote the testbench environment using UVM (Universal Verification Methodology) to validate the design module's accuracy for function simulation. Using Mentor Graphics Questasim 10.7c tool, the code was simulated. Achieved results demonstrates that the designed verification IP meets the required of the protocol of PCI Express. The testbench in UVM validate its correctness and supports the function of PCI Express Transaction Layer and Data Link Layer.