An analog decoder for concatenated magnetic recording schemes

This paper presents an all-analog iterative decoding network for an EPR4 magnetic recording system. A powerful serially concatenated architecture is considered, consisting of a simple outer code, an interleaver with reasonable size and a rate 1 EPR4 channel as inner code. The analog chip design is based on analog 0.18 /spl mu/m CMOS technology. Simulation results for both digital and analog implementations are shown. Practical implementation issues such as considerations of mismatch effects over performance are also discussed.