Design Strategies for High-resolution High-speed Flash-assisted Pipelined SAR ADCs

A preliminary study performed before the transistor level simulations of converters with challenging specifications is presented. The target converter is a pipelined SAR ADC with 18-bit resolution that operates with a conversion rate larger than 10 MS/s. Various techniques are proposed for reducing the number of SAR conversion cycles. A foreground interstage gain error calibration method is also discussed.