Analysis of an Inverter-Based CMOS Envelope Detector

This article derives the scaling factor of a sub-threshold inverter-based envelope detector. The scaling factor was simulated at the transistor-level using BSIM4 model parameters in 180 nm CMOS. A close analysis of the the calculated scaling factor shows that the minimum and the maximum of the scaling factor are within 10 percent of those obtained in simulation, suggesting that the scaling factor of the inverter-based envelope detector biased in the subthreshold region is accurately modeled.