Exploring Approximate Arithmetic Units for a Power-Efficient Kalman Gain VLSI Design

The Kalman gain (KG) equation is the key block of the Kalman filter (KF) processing. It comprises many multipliers and adders in its VLSI implementation, which is attractive for a low-power design exploring efficient arithmetic units. This work explores approximate arithmetic units to reduce power dissipation and area in the VLSI design of the KG block, maintaining an appropriate precision level for the filter application. We employ the leading one bit-based approximate (LoBA) multiplier combined with a lower-part-or (LOA) approximate adder in the main parts of the KG architecture. Our results highlight an approximate KG architecture with a decrease in power dissipation of 20.66% (1.26 times), compared with the exact one, achieving 84.85% success in identifying systems.